The present invention relates to a densely integrated semiconductor apparatus formed by a SAC (Self-Aligned Contact) method and a manufacturing method therefor, and more particularly to a semiconductor apparatus, such as a DRAM, having fine MOS (Metal Oxide Semiconductor) transistors and a manufacturing method therefor.
The entire contents of Japanese Patent Application No. 8-158379 filed on Jun. 19, 1996 and Japanese Patent Application No. 9-158464 filed on Jun. 16, 1997 are incorporated herein by reference.
The degree of integration of a highly-integrated semiconductor apparatus represented by a DRAM (Dynamic Random Access Memory) having memory cells each of which is composed of one MOS transistor and one capacitor has been raised by reducing the minimum processing size. However, a variety of self-align technologies have been developed as technologies capable of forming fine devices without influence of an accuracy of aligning patterns in order to further raise the degree of integration.
An example of the technologies above will now be described with reference to FIGS. 1A to 1D which is structured such that a contact hole for connecting a source/drain diffusion layer of a MOS transistor and a wiring layer of the same to each other is formed in a self-align manner with the gate electrode.
A gate insulator film 1, a gate electrode material 2, for example, poly crystal silicon, an oxide film 3 and an insulating film 4, such as a nitride film, are formed on a semiconductor substrate 100. Then, a lithography method and an anisotropic etching technique, such as RIE (Reactive Ion Etching) method, are employed to etch the insulating film 4, the oxide film 3 and the gate electrode material 2 so that a gate electrode is formed. Then, a sidewall oxide 3xe2x80x2 is formed by, for example, thermal oxidation, and an ion implantation method is employed to add impurities, such as arsenic, to the substrate 100 so that a source/drain diffusion layer 8 is formed. FIG. 1A shows the cross section of a semiconductor apparatus in the foregoing state.
Then, an insulating film 6, such as a nitride film, is deposited to cover the formed gate electrode.
Then, an anisotropic etching technique, such as the RIE method, is employed to etch the insulating film 6 and the gate oxide film 1 to expose the substrate 100 and leave the insulating film 6 on the side surfaces of the gate electrode 2 and the insulating film 4. Then, an ion implantation method or the like is employed to add impurities, such as arsenic, to the substrate 100 so that a source/drain diffusion layer 9 is formed. FIG. 1C shows the cross section of a semiconductor apparatus in the foregoing state. The source/drain structure having a shape composed of the diffusion layers 8 and 9 is generally called as an xe2x80x9cLDD structurexe2x80x9d and formed for the purpose of improving the reliability of a transistor.
Moreover, an interlayer dielectric film 10 is deposited. Then, a resist film 11 is applied, and an opening is formed in the resist film 11 to include a contact hole region and overlapping the gate electrode 2. For example, an anisotropic technique, such as the RIE method, is employed to etch the interlayer dielectric film 10 to expose the substrate 100 in such a manner that the resist film 11 is used as a mask so that a contact hole 12 is formed. FIG. 1D shows the cross section of the semiconductor apparatus in the foregoing state.
Then, the resist film 11 is removed, a conductive material is deposited, and then a wiring layer to be connected to the diffusion layers 8 and 9 is formed.
When the contact hole 12 is formed, etching conditions are determined in such a manner that the speed, at which the interlayer dielectric film 10 is etched, is made to be higher than the speed, at which the insulating films 4 and 6 are etched. As a result, if the pattern of the contact hole 12 overlaps the gate electrode 2 as shown in FIG. 1D, etching of the insulating films 4 and 6 can be prevented. Therefore, a structure is realized in which the gate electrode 2 is covered with the insulating films 4 and 6. As a result, short circuit between the wiring layer (not shown) and the gate electrode 2 can be prevented. The foregoing technology capable of preventing short circuit between the wiring layer and the gate electrode 2 regardless of the pattern alignment accuracy between the pattern of the contact hole 12 and that of the gate electrode 2 is called a xe2x80x9cself-align technologyxe2x80x9d.
However, the contact hole 12 is, in a dense semiconductor apparatus, formed in a region between adjacent gate electrodes. Therefore, the recent trend of raising the density of the semiconductor apparatus results in the distance between the gate electrodes being shortened. As a result, there arises a problem in that the resistance of the contact portion is strengthened excessively because a satisfactorily large area cannot be provided for the contact hole.
A method for weakening the resistance of the contact portion is available in which the thickness of the side wall 6 is reduced. However, the conventional manufacturing method, in which ion implantation for forming the drain diffusion layer 9 is performed by using the side wall 6 as the mask, results in the drain diffusion layer 9 being deeply diffused to a position below the gate electrode 2 as shown in FIG. 2 if the thickness of the side wall 6 is reduced. As a result, the effective channel length L of the transistor is shortened unintentionally. Therefore, there arises a problem in that the operation of the transistor cannot easily be controlled.
As described above, when the contact hole is formed in the self-align manner with the gate electrode, a large area cannot be provided for the contact hole because of the trend of raising the density of the semiconductor apparatus. Thus, there arises a problem in that the resistance of the contact hole is strengthened excessively. If the thickness of the side wall is reduced in order to prevent strengthening of the resistance of the contact portion, the source/drain diffusion layer formed by using the side wall as the mask is deeply diffused in the direction of the gate length. As a result, there arises a problem in that the effective gate length is shortened and the controllability of the transistor deteriorates.
An object of the present invention is to provide a method of manufacturing a highly integrated semiconductor apparatus having a fine transistor capable of reducing resistance of the contact between a wiring layer and a diffusion layer and exhibiting excellent controllability by providing a large area for a contact hole formed in a self-align manner with a gate electrode.
According to an aspect of the present invention, there is provided a method of manufacturing a semiconductor apparatus comprising the steps of: forming a gate electrode having a first insulating film laminated in the upper portion thereof on a gate insulating film formed on a semiconductor substrate; forming first diffusion layers on the semiconductor substrate by using the gate electrode as a mask; forming side insulating films on the side of the gate electrode; forming a second insulating film to cover the side insulating films; forming second diffusion layers on the semiconductor substrate by using the second insulating film on the side insulating film as a mask; forming an interlayer dielectric film over the semiconductor substrate and the gate electrode; selectively etching the interlayer dielectric film and the second insulating film to form an opening portion so as to expose the surface of the semiconductor substrate in the bottom portion of the opening portion; and forming a wiring layer connected to the exposed surface of the semiconductor substrate.
According to a second aspect of the present invention, there is provided a method of manufacturing a semiconductor apparatus comprising the steps of: forming a gate electrode having a first insulating film laminated in the upper portion thereof on a gate insulating film formed on a semiconductor substrate; forming first diffusion layers on the semiconductor substrate by using the gate electrode as a mask; forming a second insulating film on the side and upper surfaces of the first insulating film and the side surface of the gate electrode; forming second diffusion layers on the semiconductor substrate by using the second insulating film on the side wall of the gate electrode as a mask; forming an interlayer dielectric film over the semiconductor substrate; selectively etching the interlayer dielectric film and the second insulating film to form an opening portion in the gate electrode; forming a third insulating film on the side wall of the opening portion and the side wall of the gate electrode; and forming a conductive material in the opening portion.
According to the third aspect of the present invention, there is provided a method of manufacturing a semiconductor apparatus comprising the steps of: forming a gate electrode having a first insulating film laminated in the upper portion thereof on a gate insulating film formed on a semiconductor substrate; forming first diffusion layers on the semiconductor substrate by using the gate electrode as a mask; forming a first side insulating films on side walls of the gate electrode; forming a second insulating film to cover the first side insulating films forming second side insulating films on side walls of the gate electrode on the second insulating film; forming second diffusion layers on the semiconductor substrate by using the second insulating film on the first side insulating films as a mask; forming a interlayer dielectric film over the semiconductor substrate; selectively etching the interlayer dielectric film, the second insulating film and the second side insulating films to form an opening portion in the gate electrode; and forming a conductive material in the opening portion.
According to a fourth aspect of the present invention, there is provided a method of manufacturing a semiconductor apparatus comprising the steps of: forming a gate electrode having a first insulating film laminated in the upper portion thereof on first and second regions on a gate insulating film formed on a semiconductor substrate in such a manner that the interval between gate electrodes in the first region is shorter than that in the second region; forming first diffusion layers on the semiconductor substrate by using the gate electrode as a mask; forming a second insulating film to cover the gate electrode; forming second diffusion layers on the semiconductor substrate by using a portion of the second insulating film on the side insulating film which is formed on the side surface of the gate electrode as a mask; forming an interlayer dielectric film over the semiconductor substrate; selectively etching the interlayer dielectric film and the second insulating film in the first region to form a first opening portion in the gate electrode; selectively etching the interlayer dielectric film and the second insulating film in the second region to form a second opening portion in the gate electrode; and forming a conductive material in the first and second opening portions.
According to a fifth aspect of the present invention, there is provided a method of manufacturing a semiconductor apparatus comprising the steps of: forming a gate electrode having a first insulating film laminated in the upper portion thereof on first and second regions on a gate insulating film formed on a semiconductor substrate in such a manner that the interval between gate electrodes in the first region is shorter than that in the second region; forming first diffusion layers on the semiconductor substrate by using the gate electrode as a mask; forming first side insulating films on the side wall of the gate electrode; forming a second insulating film such that a space between gate electrodes on the first region is substantially plugged; forming second side insulating films on the second insulating film on the side wall of the gate electrode in the second region; forming second diffusion layers on the semiconductor substrate by using a portion of the second insulating film on the side insulating film in the side portion of the gate electrode as a mask; forming a interlayer dielectric film over the semiconductor substrate; selectively etching the interlayer dielectric film and the second insulating film in the first region to form a first opening portion in the gate electrode; selectively etching the interlayer dielectric film and the second insulating film in the second region to form a second opening portion in the gate electrode; and forming a conductive material in the first and second opening portions.
According to a sixth aspect of the present invention, there is provided a semiconductor apparatus comprising: a semiconductor substrate; a gate insulating film formed on the semiconductor substrate; first and second gate electrodes formed on the gate insulating film and respectively having first and second insulating films laminated thereon; side insulating films formed on the side walls of the first and second gate electrodes; a wiring layer formed between the first and second gate electrodes; a third insulating film for covering a predetermined portion on the first insulating film and the side insulating film opposite to the side wall of the first gate electrode adjacent to the wiring layer; a fourth insulating film for covering a predetermined portion on the second insulating film and the side insulating film opposite to the side wall of the second gate electrode adjacent to the wiring layer; a first diffusion layer formed on the two sides of a region which is formed below the first and second gate electrode and in which a channel will be formed, the first diffusion layer being formed on the surface of the semiconductor substrate; and a second diffusion layer having an end adjacent to the region in which the channel will be formed and located more apart from the region in which the channel will be formed than the end of the first diffusion layer adjacent to the region in which the channel will be formed, the second diffusion layer having a bottom portion which is deeper than the bottom portion of the first diffusion layer.
According to a seventh aspect of the present invention, there is provided a semiconductor apparatus comprising: a semiconductor substrate; first and second gate electrodes formed on the gate insulating film and respectively having first and second insulating films laminated thereon; first side insulating films formed on the side wall of the first gate electrode; second side insulating films formed on the side wall of the second gate electrode; a wiring layer formed between the first and second gate electrodes; a third insulating film for covering a predetermined portion on the first insulating film and a portion of the first side insulating films that is the side insulating film opposite to the side wall of the first gate electrode adjacent to the wiring layer; a fourth insulating film for covering a predetermined portion on the second insulating film and a portion of the second side insulating films that is the side insulating film opposite to the side wall of the second gate electrode adjacent to the wiring layer; third side insulating films formed on the third insulating film; fourth side insulating films formed on the fourth insulating film; a first diffusion layer formed on the two sides of a region which is formed below the first and second gate electrodes and in which a channel will be formed, the first diffusion layer being formed on the surface of the semiconductor substrate; and a second diffusion layer having an end adjacent to the region in which the channel will be formed and located more apart from the region in which the channel will be formed than the end of the first diffusion layer adjacent to the region in which the channel will be formed, the second diffusion layer having a bottom portion which is deeper than the bottom portion of the first diffusion layer.
According to a eighth aspect of the present invention, there is provided a semiconductor apparatus comprising: a semiconductor substrate having first and second regions; a gate insulating film formed on the semiconductor substrate; the first region on the semiconductor substrate comprising: first and second gate electrodes formed on the gate insulating film and respectively having first and second insulating films laminated thereon; a wiring layer formed between the first and second gate electrodes; a first insulating film for covering a predetermined portion on the first insulating film and the side wall of the first gate electrode opposite to the side wall adjacent to the wiring layer; a second insulating film for covering a predetermined portion on the second insulating film and the side wall of the second gate electrode opposite to the side wall adjacent to the wiring layer; a first interlayer dielectric film formed on the first insulating film; a second interlayer dielectric film formed on the second insulating film; a third insulating film formed between the first interlayer dielectric film, the first insulating film and the first gate electrode and the wiring layer; a fourth insulating film formed between the second interlayer dielectric film, the second insulating film and the second gate electrode and the wiring layer; and a first diffusion layer formed on the two sides of a region which is formed below the first and second gate electrodes and in which a channel will be formed, the first diffusion layer being formed on the surface of the semiconductor substrate; the second region on the semiconductor substrate comprising: third and fourth gate electrodes formed on the gate insulating film such that the third and fourth gate electrode are formed on the two sides of the wiring layer and the distance between gate electrodes is longer than that in the first region, the third and fourth gate electrodes respectively having fifth and sixth insulating films laminated thereon; a seventh insulating film for covering the third gate electrode; an eighth insulating film for covering the fourth gate electrode; a third interlayer dielectric film formed on the seventh insulating film; a fourth interlayer dielectric film formed on the eighth insulating film; a ninth insulating film formed between the third interlayer dielectric film and the seventh insulating film and the wiring layer; a tenth insulating film formed between the fourth interlayer dielectric film and the eighth insulating film and the wiring layer; a second diffusion layer formed on the two sides of a region which is formed below the third and fourth gate electrodes and in which a channel will be formed, the second diffusion layer being formed on the surface of the semiconductor substrate; and a third diffusion layer having an end adjacent to the region in which the channel will be formed and located more apart from the region in which the channel will be formed than the end of the second diffusion layer adjacent to the region in which the channel will be formed, the third diffusion layer having a bottom portion which is deeper than the bottom portion of the first diffusion layer.
According to a ninth aspect of the present invention, there is provided a semiconductor apparatus comprising: a semiconductor substrate having first and second regions; and a gate insulating film formed on the semiconductor substrate, the first region on the semiconductor substrate comprising: first and second gate electrodes formed on the gate insulating film and respectively having first and second insulating films laminated thereon; a plurality of first side insulating films formed on the side walls of the first and second gate electrodes; a wiring layer formed between the first and second gate electrodes; a third insulating film for covering a predetermined portion on the first insulating film and a portion of the plural first side insulating films which is the side insulating film on the first gate electrode opposite to the side wall adjacent to the wiring layer; a fourth insulating film for covering a predetermined portion on the second insulating film and a portion of the plural first side insulating films which is the side insulating film on the second gate electrode opposite to the side wall adjacent to the wiring layer; and a first diffusion layer formed on the two sides of a region which is formed below the first and second gate electrode and in which a channel will be formed, the first diffusion layer being formed on the surface of the semiconductor substrate, the second region of the semiconductor substrate comprising: third and fourth gate electrodes formed on the gate insulating film such that the third and fourth gate electrodes are formed on the two sides of the wiring layer and the distance between the gate electrodes is longer than that in the first region, the third and fourth gate electrodes respectively having fifth and sixth insulating films laminated thereon; second side insulating films formed on the side wall of the third gate electrode; third side insulating films formed on the side wall of the second gate electrode; seventh insulating film for covering a predetermined portion on the fifth insulating film and a portion of the second side insulating film which is the side insulating film on the side wall of the third gate electrode opposite to the side wall of the third gate electrode adjacent to the wiring layer; eighth insulating film for covering a predetermined portion on the sixth insulating film and a portion of the third side insulating film which is the side insulating film on the side wall of the fourth gate electrode opposite to the side wall of the fourth gate electrode adjacent to the wiring layer; fourth side insulating films formed on the seventh insulating film; fifth side insulating films formed on the eighth insulating film; a second diffusion layer formed on the two sides of a region which is formed below the third and fourth gate electrodes and in which a channel will be formed, the second diffusion layer being formed on the surface of the semiconductor substrate; and a third diffusion layer having an end adjacent to the region in which the channel will be formed and located more apart from the region in which the channel will be formed than the end of the first diffusion layer adjacent to the region in which the channel will be formed, the third diffusion layer having a bottom portion which is deeper than the bottom portion of the second diffusion layer.
According to the present invention structured as described above, there is provided a method of manufacturing a highly integrated semiconductor apparatus having a fine transistor capable of reducing resistance of the contact portion between a wiring layer and a diffusion layer and exhibiting excellent controllability by providing a large area for a contact hole formed in a self-align manner with a gate electrode.
By applying the present invention structured as described above to a DRAM, the effective channel length of fine transistors forming the peripheral circuit or the like can be maintained. Moreover, a satisfactory large area can be provided for a contact hole even in a region, such as a memory cell, in which the pattern density is high.
Additional objects and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out in the appended claims.